Nonvolatile semiconductor memory device
US9035371B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Jul 6, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region provided with a plurality of memory cells, and a peripheral region provided around the memory cell region. The device includes: a foundation layer provided in the memory cell region and in the peripheral region, the foundation layer including a plurality of wiring layers and a plurality of device elements; and a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers and a plurality of intermediate layers alternately stacked. The peripheral region includes an interlayer insulating film provided on the stacked body; and an electrode pad provided on the interlayer insulating film and electrically connected to one of the plurality of wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.