3D IC with serial gate MOS device, and method of making the 3D IC
US9035464B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 30, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.