Routing layer for mitigating stress in a semiconductor die
US9035471B2 · kind B2 · utility
2Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Feb 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.