Circuit for controlling variation in frequency of clock signal
US9035683B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1077
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.