Interconnection substrate design supporting device, method of designing interconnection substrate, program, and interconnection substrate
US9036365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2010 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Oct 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09718
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.