Global reset with replica for pulse latch pre-decoders
US9036446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Mar 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.