Post-cursor locking point adjustment for clock data recovery
US9036757B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2014 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Sep 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.