Methods and devices for implementing all-digital phase locked loop
US9036763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Mar 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An all-digital phase locked loop includes a time to digital converter that determines a fractional portion of a phase count. The time to digital converter has a quantization error that may be caused by phase noise, delay errors or skew errors. Several methods and devices may reduce the quantization error. A noise source may add dithering to the reference clock at an input of the time to digital converter. A digital processor may use two successive rising edges of the oscillator signal to count time delays of the time to digital convertor to the reference clock, and uses these counts to determine a ratio of the time delays and the time period of the oscillator signal for controlling a digitally controlled oscillator. A radio frequency counter circuit detects whether the oscillator signal leads or lags the reference clock because of skew and generates a phase signal to correct the skew.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.