Shared load-store unit to monitor network activity and external memory transaction status for thread switching
US9037836B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2011 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Aug 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.