Synchronizing data transfer from a core to a physical interface
US9037893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2013 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Dec 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.