Systems and methods for error checking and correcting for memory module
US9037941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2012 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Apr 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for error checking and correcting (ECC) in a memory module including at least one memory unit are provided. The method includes the steps of: receiving input data from the memory unit; performing, by a first ECC module, a first ECC operation to the input data and generating a decoding result which indicates whether decoding was successful; and determining whether to activate a second ECC module to perform a second ECC operation to the input data according to the decoding result, wherein the first and second ECC modules respectively utilize a first method and a second method, wherein the first method applies a ECC with a first fault tolerant quantity for error correction and the second method applies a ECC with a second fault tolerant quantity for error correction, and the second fault tolerant quantity is larger than the first fault tolerant quantity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.