VCSEL packaging
US9038883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Sep 7, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.