Patent · US Active

Method for processing a carrier, method for fabricating a charge storage memory cell, method for processing a chip, and method for electrically contacting a spacer structure

US9040375B2 · kind B2 · utility

0Cited by
4References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 28, 2013
Grant dateMay 26, 2015
Priority date
Expiry dateJul 7, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/037
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.