Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods
US9040378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.