Three-dimensional vertically interconnected structure and fabricating method thereof
US9040412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.