Partial reconfiguration and in-system debugging
US9041431B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jan 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17756
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.