De-noise circuit and de-noise method for differential signals and chip for receiving differential signals
US9041490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Apr 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45618
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.