Method and apparatus for calibration of successive approximation register analog-to-digital converters
US9041569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/466
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation register (SAR) ADC includes an SAR comparator circuit including first and second inputs, a control input, and first and second outputs. The SAR comparator circuit further includes a plurality of capacitors coupled to the first and second inputs and includes a plurality of switches configured to couple the plurality of capacitors to one of a first voltage and a second voltage. The SAR ADC further includes a calibration circuit coupled to the first and second outputs and to the control input of the SAR comparator. The calibration circuit is configured to control the plurality of switches to selectively couple the plurality of capacitors to one of the first and second voltages to provide a calibration signal to the SAR comparator circuit. The calibration circuit is configured to calibrate the SAR comparator based on corresponding output signals at the first and second outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.