Analog-to-digital conversion in pixel arrays
US9041579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jan 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/123
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.