Memory controller and method of calibrating a memory controller
US9042188B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller transmits a data signal, a data strobe signal and a mask signal to a memory, wherein each transition of the data strobe signal indicates a sample point for the data signal and the mask signal indicates a validity of the data signal. A mask signal training procedure is carried out comprising three steps. Writing first and second values to the memory for a predetermined plurality of transitions of the data strobe signal with the mask signal set to indicate that the first data signal is valid and the second data signal is valid except for a selected transition of the predetermined plurality. Reading from the memory for the predetermined plurality of transitions of the data strobe signal. Determining a timing offset for the mask signal for which the value read at the selected transition matches the first value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.