Serial peripheral interface having a reduced number of connecting lines
US9042274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2009 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40006
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An electronic communication system including at least one first communication unit and one second communication unit which are connected to one another by means of at least one first data line. The communication system has a data transmission protocol according to which, in at least one first data transmission mode for synchronized data transmission, the first communication unit transmits a data request signal or a clock signal to the second communication unit via the first data line at least once and the second communication unit transmits a data signal to the first communication unit via the first data line in response to the data request signal or the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.