Techniques for connected component labeling
US9042652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Dec 25, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus may include a memory, a processor circuit, and a connected component labeling module. The connected component labeling module may be operative of the processor circuit to determine one or more connected components during reading of an image comprising a multiplicity of pixels from the memory, assign a label to a plurality of pixels of the multiplicity of pixels, generate one or more label connections for a respective one or more labels, each label connection linking a higher label to a lowest label for the same connected component, and write to the memory for each label of the one or more labels a lowest label as defined by the label connection for the each label after a label is assigned to each pixel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.