Reducing peak current in memory systems
US9043590B2 · kind B2 · utility
1Cited by
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14Claims
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Key dates
| Filing date | Oct 16, 2013 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Oct 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells, a token input interface, a token output interface and control circuitry. The control circuitry is configured to accept a storage command, to condition execution of at least a part of the storage command on a presence of a token pulse on the token input interface, to execute the storage command, including the conditioned part, in the memory cells upon reception of the token pulse on the token input interface, and to reproduce the token pulse on the token output interface upon completion of the execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.