Method for enhancing memory fault tolerance
US9043638B1 · kind B1 · utility
5Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Nov 14, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various examples of the present technology provide systems and methods for testing whether there is any memory error in a server system, determining physical memory addresses corresponding to a detected memory error on one or more memory devices of the server system, and preventing the physical memory addresses corresponding to the detected memory error from accessing by an operating system, application programs, and/or other components of the server system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.