Data manipulation on power fail
US9043642B2 · kind B2 · utility
2Cited by
9References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2011 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jul 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a power isolation and backup system. When a power fail condition is detected, temporary storage is flushed to an SDRAM. After the flush, interfaces are halted, and power is removed from most of the chip except the SDRAM subsystem. The SDRAM subsystem copies data from an SDRAM to a flash memory. On the way, the data may be encrypted, and/or a data integrity signature calculated. To restore data, the SDRAM subsystem copies data from the flash memory to the SDRAM. On the way, the data being restored may be decrypted, and/or a data integrity signature checked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.