Avoiding processing flaws in a computer processor triggered by a predetermined sequence of hardware events
US9043654B2 · kind B2 · utility
1Cited by
11References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 7, 2012 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Jun 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.