Conducting verification in event processing applications using formal methods
US9043746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2011 |
| Grant date | May 26, 2015 |
| Priority date | — |
| Expiry date | Mar 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4498
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.