Patent · US Active

Processing error detection within pipeline circuitry

US9047184B2 · kind B2 · utility

3Cited by

5References

18Claims

0Family size

Assignee

Arm Limited · GB

Inventors

David Michael Bull · Balsham, GB
Shidhartha Das · Cambourne, GB
Paul Nicholas Whatmough · Cambridge, GB

Key dates

Filing date	Jul 13, 2012
Grant date	Jun 2, 2015
Priority date	—
Expiry date	Aug 22, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/1052
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes processing pipeline circuitry comprising a plurality of pipeline stages separated by respective signal value storage circuitry. Timing detection circuitry to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.