System and method for tolerating a failed page in a flash device
US9047214B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 2012 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | May 22, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7209
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application. A page is associated with a set of primary ECC codewords, and a page stripe is associated with a set of secondary codewords and primary over secondary parity (PoSP) ECC codewords. Two or more page stripes can form a page grid, wherein the page grid is associated with a group of tertiary ECC codewords, wherein the last page stripe of the page grid has a reduced payload capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.