Patent · US Active

System and method for analog verification IP authoring and storage

US9047424B1 · kind B1 · utility

4Cited by

2References

23Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Mark D. Baker · Marietta, US
Donald J. O'Riordan · Sunnyvale, US
Keith Dennison · Edinburgh, GB

Key dates

Filing date	Oct 25, 2013
Grant date	Jun 2, 2015
Priority date	—
Expiry date	Oct 28, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06F2115/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.