Patent · US Active

Timing signal adjustment for data storage

US9047934B1 · kind B1 · utility

5Cited by

0References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Bee Yee Ng · Bandar Jengka, MY
Hee Kong Phoon · Bagan Serai, MY
Beng Lee Ooi · Kangar, MY

Key dates

Filing date	Nov 13, 2013
Grant date	Jun 2, 2015
Priority date	—
Expiry date	Nov 13, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/0037
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a delay circuit, a buffer circuit, and a storage circuit. The delay circuit delays a first timing signal to generate a second timing signal. The buffer circuit generates a third timing signal for transmission to an external device. The third timing signal is generated based on the first timing signal. The external device provides data to the integrated circuit based on the third timing signal. The storage circuit captures the data transmitted from the external device in response to the second timing signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.