Patent · US Active

Semiconductor device with normally off and normally on transistors

US9048119B2 · kind B2 · utility

6Cited by

17References

9Claims

0Family size

Assignee

RENESAS ELECTRONICS CORPORATION · JP

Inventors

Takamitsu Kanazawa · Takasaki, JP
Satoru Akiyama · Tokyo, JP

Key dates

Filing date	Jun 4, 2013
Grant date	Jun 2, 2015
Priority date	—
Expiry date	Jun 4, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2017/6875
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.