Three-dimensional gate-wrap-around field-effect transistor

US9048330B2 · kind B2 · utility

Assignee

• The Board of Regents of the University of Texas System · US

Inventors

• Jack Lee · Austin, US
• Fei Xue · Sunnyvale, US

Key dates

• Filing date: Aug 28, 2013
• Grant date: Jun 2, 2015
• Expiry date: Aug 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6757

Abstract

A three-dimensional Gate-Wrap-Around Field-Effect Transistor (GWAFET). The GWAFET includes a substrate of III-V semiconductor material. The GWAFET further includes one or more channel layers with a gate wrapped around these one or more channel layers. Additionally, the GWAFET includes a barrier layer residing on the top channel layer with a layer of doped III-V semiconductor material residing on each end of the barrier layer. A source and drain contact are connected to the layer of doped III-V semiconductor material as well as to the multiple channels in the embodiment with the GWAFET including multiple channel layers. By having such a structure, integration density is improved. Furthermore, electrostatic control is improved due to gate coupling, which helps reduce standby power consumption. Furthermore, by using III-V semiconductor material as opposed to silicon, the current drive capacity is improved.