Shift register-based layered low density parity check decoder
US9048867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2013 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1171
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.