Apparatus, system, and method for timing recovery
US9049001B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2013 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | May 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0025
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.