Terminations and couplings between chips and substrates
US9049791B2 · kind B2 · utility
3Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2013 |
| Grant date | Jun 2, 2015 |
| Priority date | — |
| Expiry date | Jul 3, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.