Multi-core processor system, control program, and control method
US9052993B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jun 27, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/283
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.