System and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life
US9053036B2 · kind B2 · utility
6Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Nov 26, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Oct 17, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.