Non-sequential transfer of data from a memory
US9053052B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Jan 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example, a direct memory access controller includes a memory interface, a requestor interface, and an address generator. The memory interface is configured to cause a memory to provide at least a subset of data stored in the memory. The requestor interface is configured to receive a request for a consecutively addressed subset of the data stored in the memory to be provided in a non-consecutive order. The address generator is in communication with the requestor interface and the memory interface. The address generator is configured to, based on the request, sequentially generate non-consecutive addresses of the requested subset of the data to cause the memory to provide the requested subset of data in the requested non-consecutive order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.