Flash memory with integrated ROM memory cells
US9053791B2 · kind B2 · utility
0Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Aug 7, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.