Semiconductor device and manufacturing method thereof
US9053944B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 2014 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Feb 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a plurality of closely spaced fins each coated at its top and sidewalls with a SiGe layer used for improving charge carrier mobility in a channel portion of the device. The sidewalls of the closely adjacent Fins are selectively thinned so as to prevent an undesired bridging of SiGe material between immediately adjacent ones of the Fins. A method of manufacturing the same comprises: providing a substrate having a plurality of tri-gate transistors, at least two fins of the tri-gate transistors being closely adjacent to each other, where respective top and sidewall surfaces of the fins are coated with a SiGe layer; performing a tilted ion implantation on the SiGe coated fins so as to partially convert the SiGe material into a predetermined etch resistant material (e.g., and oxide of the SiGe); and etching away the non-converted sidewall parts of the SiGe coating layers so as to provide greater spacing between the immediately adjacent sidewalls of the SiGe coated fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.