Monolithic integration of photonics and electronics in CMOS processes
US9053980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Feb 2, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.