Smart diagnosis and protection circuits for ASIC wiring fault conditions
US9054517B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Mar 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H11/006
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises an internal circuit coupled between a power line and ground and an output buffer coupled to the internal circuit; wherein the output buffer provides an output signal. The ASIC includes a fault detection circuit coupled between the power line and ground; and a first protection block configured to receive a first control signal from the fault detection circuit. The first switch is coupled to the power line, the output buffer and the internal circuit. The first protection block prevents current from flowing between the power line and ground when a fault condition is detected. The ASIC further includes a second protection block configured to receive a second control signal from the fault detection circuit, wherein the second protection block is coupled to the output signal, the power line and ground. The second protection block prevents current from flowing between the power line and ground or the power line and the output line when a fault condition is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.