Reducing a settling time after a slew condition in an amplifier
US9054657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2013 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Dec 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45512
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an amplifier, a first stage receives a differential input voltage, which is formed by first and second input voltages, and outputs a first differential current in response thereto on first and second lines having respective first and second line voltages. A second stage receives the first and second line voltages and outputs a second differential current in response thereto on third and fourth lines having respective third and fourth line voltages. A third stage receives the third and fourth line voltages and outputs an output voltage in response thereto. A slew boost circuit detects a slew condition, in which a threshold difference arises between the first and second input voltages, and outputs a slew current in response thereto for maintaining a slew rate of the output voltage during the slew condition. The first stage includes circuits for reducing a variable difference between the first and second line voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.