Patent · US Active

High speed duty cycle correction and double to single ended conversion circuit for PLL

US9054681B2 · kind B2 · utility

0Cited by

8References

7Claims

0Family size

Assignee

CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE · CN

Inventors

Youhua Wang · Chongqing, CN
Junan Zhang · Nan'an District, CN
Dongbing Fu · Chongqing, CN
Gangyi Hu · Chongqing, CN
Jun Liu · Taichung, TW
Ruzhang Li · Chongqing, CN
Guangbing Chen · Tangxia, CN

Key dates

Filing date	Aug 23, 2011
Grant date	Jun 9, 2015
Priority date	—
Expiry date	Feb 22, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1565
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The present invention pertains to a high speed duty cycle correction and double to single ended conversion circuit for PLL, comprising a reshaper stage, a single-edge detection circuit and a duty cycle restorer. The present invention introduces a way to convert double-ended output of PLL VCO into single-ended signal and adjust duty cycle of PLL VCO's output waveform by 50%, so that the circuit can output single ended clock signal with 50% duty cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.