RFI mitigation using burst timing
US9054908B2 · kind B2 · utility
1Cited by
0References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Jun 9, 2015 |
| Priority date | — |
| Expiry date | Dec 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03828
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A chip is provided to include a circuit to transmit one or more data bursts, where the circuit includes burst timing logic to insert gaps of a determined length between adjacent data bursts to reduce noise at a desired frequency, where the length of each gap is to be determined based on energy of a preceding burst and a current burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.