Modular low-power unit with analog synchronization loop usable with a low-dropout regulator
US9058049B2 · kind B2 · utility
1Cited by
8References
25Claims
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Key dates
| Filing date | Apr 18, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/565
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A low-power-mode unit connected in parallel with a low-dropout regulator to provide a low-power mode includes a power P-MOS transistor, a differential amplifier, and an analog synchronization loop. The analog synchronization loop is configured to add a variable voltage offset depending on a total current at the output such that, in a high-power mode, the low-power unit current flowing through the P-MOS transistor is not zero, while being substantially smaller than the low-dropout regulator current flowing through the low-dropout regulator, and smaller than a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.