Vector-based matching circuit for data streams
US9058108B2 · kind B2 · utility
0Cited by
5References
15Claims
0Family size
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Key dates
| Filing date | Dec 16, 2011 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | May 31, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/276
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described relating to a matcher that inputs partial vectors at a rate of 1 per clock cycle and delivers complete vectors at the output with an indication per vector of its validity. The matcher can copy a maximum number of valid elements from an input queue to target vector in-order each clock cycle and eliminate copied elements from the input queue. The completely filled target vectors are paired with the complete data vectors and outputted as composite vectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.