Per-rank channel marking in a memory system
US9058276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2013 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Dec 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.