Method and system for inserting software processing in a hardware image sensor pipeline
US9058668B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2007 |
| Grant date | Jun 16, 2015 |
| Priority date | — |
| Expiry date | Mar 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0096
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Image data may be processed via one or more stages by a hardware image sensor pipeline (ISP) wherein one or more software processing steps may be inserted at any point within the hardware ISP. Output from any stage of the hardware ISP may be stored in memory. Stored hardware ISP output may be retrieved from memory and processed via one or more software processes. Results from the one or more software processes may be stored in memory and communicated to any stage of the hardware ISP for additional processing. In this regard, the hardware ISP and one or more processors may simultaneously process portions of image data. In addition, the hardware ISP and the one or more processors may be integrated within a chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.